Mixed signal systems typically consist of a digital core, including a CPU or digital signal processor (DSP), and various memory blocks. The core may be surrounded by analog interface electronics such as I/O, digital-to-analog and analog-to-digital converters, and RF front ends, for example. Micro-electronic circuit systems can also be a centralized analog core, including a receiver and/or a transmitter complex, which are surrounded by a variety of digital circuitry. A CMOS micro-electronic circuit chip includes CMOS digital and analog circuits. The analog circuits are constrained to function in tandem with the digital design, which is dictated by CMOS evolution. In particular, the harmonic-distortion components of transistors (or noise) increase drastically as power supply voltages for digital circuits decrease.
As power supply voltages continue to decrease with advancing technologies, it is becoming increasingly difficult to raise the performance of analog circuits. This is because the threshold voltages of the various analog devices cannot be scaled along with the decreasing power supply voltages. In order to increase performance for certain high-speed critical circuits, high supply voltages are often necessary, while using the low threshold weak devices wherever possible to get maximum circuit overdrive. Moreover, systems developed under new technologies are optimized to be powered by a low voltage power supply, but are still required to be compatible to old legacy systems, which operate in a high voltage power supply environment. Thus, analog circuit designers are faced with the challenge of preventing low threshold weak devices from being overstressed, or broken down, and preventing hot electron performance degradation in a multiple power supply system.
Gate leakage current in semiconductor transistor devices mainly depends on gate to substrate voltage, source or drain bias voltage, and gate dielectric thickness and size. As the MOS technology advances, gate dielectric becomes thinner and is increasingly exposed to gate leakage problems, especially when the gate dielectric (e.g. SiO2) is stressed at high voltage. The net effect of gate leakage is undesired and uncontrollable input bias current, gate leakage mismatch, and shot noise. The input bias currents caused by gate leakage are very similar to the base currents of bipolar devices, except the width and length of the MOS devices can be optimized. The input impedance of a MOS device consists of the conventional input capacitance and a parallel tunnel resistance due to gate leakage. With respect to 90 nm scale devices, for signal frequencies higher than 1 MHz, the input impedance is capacitive and the MOSFET behaves as a conventional MOS. At lower signal frequencies, the input impedance is resistive and the gate leakage is dominant. Therefore, thin-dielectric MOS capacitances are not suitable for certain low-frequency applications like PLL filters and hold circuits.
Gate leakage mismatch typically exceeds conventional threshold mismatch tolerances. Matching gate leakage usually limits the achievable level of performance for analog circuits. One way to reduce the threshold related mismatch effect is to increase the chip area. However, gate leakage mismatch then acts as an extra spread source and places an upper bound on the area that can be used to decrease threshold mismatch. When increasing the chip area, the conventional threshold spreading contribution decreases, but the gate leakage spread contribution increases. As the result, the maximum usable transistor area is limited by gate leakage spread. The problem becomes more significant in the 65 nm and 45 nm scale generations. Typically, the maximum area is about 103 μm2 or less. To reduce gate leakage, one design strategy involves providing a high voltage to critical parts of the circuitry so that these circuits can be built with transistors having thicker gate dielectrics. MOS lifetime is dominated by vertical and lateral electric fields and electric fields across the junctions. Three lifetime determining mechanisms that relate to these electric fields are denoted as dielectric breakdown, hot-carrier degradation, and junction breakdown. However, this design strategy does not work with analog circuits. In order to achieve proper circuit performance, some analog circuit devices must be low threshold weak devices.
Various methods to reduce voltage stress on the digital I/O circuits have been proposed. One such method involves using cascade circuits to protect devices from high voltage stress. However, this method is not useful for analog circuits because all the signals in the analog circuits do not swing from rail to rail.
Another method to avoid hot carrier related problems involves delaying turning on a transistor until the drain and source have dropped below the characteristic hot carrier operation voltage. However, this method ignores the problem of gate dielectric stress.
Still another method to avoid hot carrier problems involves cascading devices and biasing intermediate node voltages to half the power supply level. This method only works well when the power supply level is sufficiently higher than the sum of the threshold levels of the cascaded devices. Otherwise, certain analog devices cannot operate properly due to lack of power supply headroom. Further, as the power supply level is reduced, and the technology is further scaled down, this method becomes impracticable. This method also fails to address how to avoid gate dielectric stress.